May 7, 2012
6:16 pm
by: admin

Hot Swap Models

Hot Swap defines three levels of Hot Swap functionality as shown in Table 10-2. These are differentiated mainly in how the hardware and software connection processes are carried out. Basic Hot Swap is the simplest in terms of its impact on both boards and backplanes and, not surprisingly, has the least capability. The Basic Model operates much like Hot Plug in that the operator must interact with

Table 10-2: Hot Swap models.

System Type

Hardware Connection

Software Connection

Basic Hot Swap Full Hot Swap

High Availability

Automatic in HW Automatic in HW

Controlled by SW

Manually by Operator

Controller (Automatic) by Software

Controller (Automatic) by Software

The system to effect software connection and disconnection and the functions must be performed in the correct sequence for proper system operation.

Full Hot Swap provides facilities that automatically notify the system software that a board is either being plugged in or removed. This allows the software connection process to be automated.

High Availability adds software control of the hardware connec­tion process in order to detect and, hopefully, isolate faulty boards. Each model builds on the facilities of the preceding simpler one.

The three models lead to several definitions of both platforms and boards as shown in Figure 10-2. The Hot Swap architecture is designed to allow all combinations of platforms and boards to inter – operate. The system model is determined by the features of the lowest common denominator.

Platforms come in three flavors:

Board

¦ Non-Hot Swap platforms lack any or all of the elements required to support Hot Swap.

Platform


Hardware Connection Layer

Compact PCI Bus

Full Hot Swap

HWConn Control

High

Availability

Conventional Compact PCI HW

SW Conn Control

Compact PCI Bus

Hardware Connection Layer

HW Hot Swap Control

Basic Hot Swap

Compact PCI Bus

Conventional Compact PCI HW

Non Hot Swap

Non Hot Swap


Conventional Compact PCI HW

Figure 10-2: Hot Swap interoperability.


¦ Hot Swap platforms contain all the required Hot Swap elements.

¦ High Availability (HA) platforms contain the required Hot Swap elements plus a platform-specific implementation for Hardware Connection Control

Likewise, boards come in three flavors:

¦ Non-Hot Swap boards don’t have a Hardware Connection Layer.

¦ Basic Hot Swap boards have the Hardware Connection Layer.

¦ Full Hot Swap boards add the Software Connection Control resources.

The various combinations of platforms and boards lead to the set of system configurations shown in Table 10-3. The Hot Swap specifi­cation layers on top of the basic Compact PCI Specification, providing backward compatibility and allowing Hot Swap to operate in a con­ventional platform. This configuration does not support Hot Swap.

Table 10-3: System configurations.

Platform Type

Board Type

System

Non-Hot Swap

Non-Hot Swap

Conventional Compact PCI

Basic Hot Swap

Full Hot Swap

Hot Swap

Non-Hot Swap

Conventional CompactPCI

Basic Hot Swap

Basic Hot Swap System

Full Hot Swap

Full Hot Swap System

High Availability

Non-Hot Swap

Conventional CompactPCI

Basic Hot Swap

High Availability System

Full Hot Swap

A Hot Swap platform can have a mixture of Hot Swap and Non-Hot Swap boards. The Non-Hot Swap elements are of course not Hot Swappable but otherwise function normally. The Hot Swap boards are swappable. Note that HA functionality is a function of the platform and not the boards.

The specification cautions that mixing Basic and Full Hot Swap boards can create an environment that "could be confusing to the operator. If some boards configure automatically, and some require operator intervention, the operator may incorrectly insert (or extract) a board."

Figure 10-3 shows the overall architectural model encompassing both hardware and software. Note the Hot Plug Service and Hot Plug System Driver. These are essentially the same elements defined by PCI Hot Plug.


API

Hot Plug Service

HA Service

Operating System

HA System Driver

Software Layers

Device Driver

Device Driver

Device Driver

Hardware Abstraction

SW Connection Control HAL

Drivers

Hot Plug System Driver

HW Connection Control HAL


Compact PCI Bus

HW Connection Control

Platform Hardware

SW Connection Control

Board

Hardware Connection Layer

Hardware

Conventional Compact PCI HW

Basic Hot Swap Full Hot Swap High Availability

Figure 10-3: Hot Swap system architecture.


Posted in Hot Swap Models

May 7, 2012
6:16 pm
by: admin

Backplane Design Rules

In the course of developing the CompactPCI specification, extensive simulations were done to verify conformance with the basic PCI electrical specifications. Pinout was optimized with respect to common mode noise and crosstalk as well as to allow easy hookup to the "preferred" signal ordering defined in the PCI specification for peripheral chips.

Several configurations were analyzed using both best and worst case buffers. These were:

¦ Fully loaded

¦ "Moderately" loaded

¦ Lightly loaded

The simulation results led to recommendations and rules for backplane and adapter card design.

The PCI specification has no requirement for the impedance of an unloaded motherboard. However the tighter electrical require­ments of Compact PCI require that an unloaded backplane have an impedance of 65 ohms ±10%.

Simulation revealed that a lightly loaded 8-slot configuration with a system slot board and a peripheral board loaded adjacent to the system slot using the strongest case drivers had V(I/O)

Signal

GND

Figure 9-7: Backplane termination for lightly loaded case.

A problem owing to the long unterminated stub presented by the un­loaded connectors. This was solved with a fast Schottky diode termina­tion at the far end of the backplane trace or on a termination board plugged into the farthest slot (see Figure 9-7).

Posted in Backplane Design Rules

May 7, 2012
6:16 pm
by: admin

PCI Connector (continued)

Pin

Side B<2)

Side A

71

AD[59]

AD[58]

72

AD[57]

Gnd

73

Gnd

AD[56]

74

AD[55]

AD[54]

75

AD[53]

+Vio (1)

76

Gnd

AD[52]

77

AD[51]

AD[50]

78

AD[49]

Gnd

79

+Vio (4)

AD[48]

80

AD[47]

AD[46]

81

AD[45]

Gnd

82

Gnd

AD[44]

83

AD[43]

AD[42]

84

AD[41]

+Vio (1)

85

Gnd

AD[40]

86

AD[39]

AD[38]

87

AD[37]

Gnd

88

+Vio (1)

AD[36]

89

AD[35]

AD[34]

90

AD[33]

Gnd

91

Gnd

AD[32]

92

Reserved

Reserved

93

Reserved

Gnd

94

Gnd

Reserved


Posted in PCI Connector (continued)

May 7, 2012
6:16 pm
by: admin

Electrical Implementation

The electrical differences between conventional PCI and CompactPCI involve some additional signals, routing of point-to – point and interrupt signals and design rules for boards and backplanes derived from the simulations.

Posted in Electrical Implementation

May 7, 2012
6:16 pm
by: admin

Class Codes

Class/ Subclass

Programming Interface

Class 00

Device predates class code definitions

00

Non-VGA devices

01

VGA devices

Class 01

Mass storage controllers

00

SCSI controller

01

IDE controller

Xx

See Note 1

02

Floppy disk controller

03

IPI bus controller

04

RAID controller

Class 02

Network controllers

00

Ethernet

01

Token Ring

02

FDDI

03

ATM

04

ISDN

Class 03

Display controllers

00

VGA/8514

01 VGA-compatible

02 8514-compatible

01

XGA

02

3-D controller

Class 04

Multimedia devices

00

Video

01

Audio

02

Computer telephony

Note

1. IDE Programming interface: Bit 0 Operating mode (primary)

Bit 1 Programmable indicator (primary)

Bit 2 Operating mode (secondary)

Bit 3 Programmable indicator (secondary)

A

Bit 7 Master IDE device


Programming interface

Memory controllers

RAM Flash

Bridge devices

Host bridge ISA bridge EISA bridge MCA bridge PCI to PCI bridge

0 PCI to PCI bridge

1 Supports subtractive decode PCMCIA bridge

NuBus bridge Cardbus bridge

RACEway bridge

Simple communication controllers

0 Generic XT-compatible serial controller

1 16450-compatible serial controller

2 16550-compatible serial controller

3 16650-compatible serial controller

4 16750-compatible serial controller

5 16850-compatible serial controller

16950-compatible serial controller

0 Parallel Port

1 Bi-directional parallel port

2 ECP 1.X compliant parallel port

3 IEEE 1284 controller FE IEEE 1284 target device Multiport serial controller

0 Generic modem

1 Hayes compatible, 16450 interface (2)

2 Hayes compatible, 16550 interface (2)

3 Hayes compatible, 16650 interface (2)

Class / Subclass

Class 05

00 01

Class 06

00 01 02

3

4

5

6

7

8

Class 07

00

01

02 03

4 Hayes compatible, 16750 interface (2)


Note

2. First BAR (10h) maps appropriate compatible register set. Registers can be either memory or I/O mapped


Class / Subclass

Programming Interface

Class 08

Generic system peripherals

00

Interrupt controllers

00 Generic 8259

01 ISA PIC

02 EISA PIC

03 I/O APIC (3)

01

DMA controllers

00 Generic 8237

01 ISA DMA

02 EISA DMA

02

Timers

00 Generic 8254

01 ISA system timer

02

EISA system timer (two timers)

03

Real-time clock

00 Generic RTC

01 ISA RTC

04

Generic PCI Hot-Plug controller

Class 09

Input devices

00

Keyboard controller

01

Digitizer (pen)

02

Mouse controller

03

Scanner controller

04

Gameport

00 Generic

02 See note 4

Class OA

Generic docking station

Class OB

Processors

00

386

01

486

02

Pentium

10

Alpha

20

Power PC

30

MIPS

40

Co-processor

Note

First BAR (10h) requests minimum 32 bytes non-prefetchable space. Base+0 = I/O Select, Base+10h = I/O Window. See Intel 82420/82430 PCIset EISA Bridge Databook (#290483-003) for more details

"Legacy" game port. Byte at offset 01h aliases to byte at offset 00h


Class / Subclass

Programming interface

Class 0C

Serial bus controllers

00

IEEE 1394

00 Firewire

10 Open HCI specification

01

ACCESS. bus

02

SSA

03

USB

00 Universal Host Controller specification

10 Open HCI specification

80 No specific programming interface

FE USB device, not controller

04

Fibre Channel

05

System Management Bus

Class 0D

Wireless controllers

00

IRDA controller

01

Consumer IR controller

10

RF controller

Class 0E

Intelligent I/O controllers

00

Xx I2O Architecture Specification 1.0

1.

Message FIFO at offset 40h

Class 0F

Satellite communication controllers

00

TV

01

Audio

02

Voice

03

Data

Class 10

Encryption/decryption

00

Network & computing en/decryption

10

Entertainment en/decryption

Class 11

Data acquisition & signal processing

00

DPIO modules

Note

5. For all classes except 00, subclass 80h means "other".


APPE

Posted in Class Codes

May 7, 2012
6:16 pm
by: admin

Compact PCI Connectors – P1

Pin

A

B

C

D

E

25

+5V

REQ64#

ENUM#

+3.3V

+5V

24

AD[01]

+5V

+Vio (1)

AD[00]

ACK64#

23

+3.3V

AD[04]

AD[03]

+5V

AD[02]

22

AD[07]

Gnd

+3.3V

AD[06]

AD[05]

21

+3.3V

AD[09]

AD[08]

M66EN

C/BE[0]

20

AD[12]

Gnd

+Vio (1)

AD[11]

AD[10]

19

+3.3V

AD[15]

AD[14]

Gnd

AD[13]

18

SERR#

Gnd

+3.3V

PAR

C/BE[1]

17

+3.3V

SCL(5)

SDA(5)

Gnd

PERR#

16

DEVSEL#

Gnd

+Vio (1)

STOP#

LOCK#

15

+3.3V

FRAME#

IRDY# BDSEL# TRDY#

14 – 12 KEYWAY

11

AD[18]

AD[17]

AD[16]

Gnd

C/BE[2]

10

AD[21]

Gnd

+3.3V

AD[20]

AD[19]

9

C/BE[3] IDSEL AD[23]

Gnd

AD[22]

8

AD[26]

Gnd

+Vio

AD[25]

AD[24]

7

AD[30]

AD[29]

AD[28]

Gnd

AD[27]

6

REQ#

Gnd

+3.3V

CLK

AD[31]

5

Bus Res

Bus Res

RST#

Gnd

GNT#

4

Pwr(5)

HLTHY#

+Vio (1)

INTP

INTS

3

INTA#

INTB#

INTC#

+5V

INTD#

2

TCK

+5V

TMS

TDO

TDI

1

+5V

-12V

TRST#

+ 12V

+5V

Notes

1. Vio is +5V in 5V signaling environments and +3.3V in 3.3V signaling environments

2. Side B = Component Side, Side A = Solder Side

3. System slot only.

4. "Res" = Reserved, "Bus Res" = Reserved and bussed to all slots in the segment.

5. Power Management Bus, defined by PICMG 2.9, Compact PCI System Management Specification

6. = Long pin = Short pin



[1] It’s not clear from the specification who gets to assign these keywords.

[2] The specification goes on to say "One or more of the Vx, Yx and RW items are required." I take this to mean that unless one of these items is present, there’s no point in having a read/write section. The read/write section doesn’t include a checksum.

[3] The specification text never explicitly says that logical slots proceed in numerical order starting from the system slot but the backplane drawings clearly infer it.

[4] The specification is rather vague about the DEG# and FAL# signals. In particular, it doesn’t say anything about relative timing. It would be nice, for example, if the FAL# signal were asserted a few milliseconds before the supply actually failed to give the host processor some time to do something about it.

Posted in Compact PCI Connectors - P1

May 7, 2012
6:16 pm
by: admin

Hot Swap Processes

Hot Swap can be described in terms of three processes. These processes can be described further as a procession of states. Each succeeding state is dependent on the success of the preceding state. The processes are described below in terms of board insertion where the order is:

1. Physical Connection

2. Hardware Connection

3. Software Connection

Board extraction operates in the reverse order:

1. Software Disconnection

2. Hardware Disconnection

3. Physical Extraction

Posted in Hot Swap Processes

May 7, 2012
6:16 pm
by: admin

Compact PCI Connectors – P2

Pin

A

B

C

D

E

22

GA[4]

GA[3]

GA[2]

GA[1]

GA[0]

21

CLK6 (3)

Gnd

Res (4)

Res

Res

20

CLK5 (3)

Gnd

Res

Gnd

Res

19

Gnd

Gnd

Res

Res

Res

18

Bus Res

Bus Res

Bus Res

Gnd

Bus Res

17

Bus Res

Gnd

PRST#

REQ6# (3)

GNT6# (3)

16

Bus Res

Bus Res

DEG#

Gnd

Bus Res

15

Bus Res

Gnd

FAL#

REQ5# (3)

GNT5# (3)

14

AD[35]

AD[34]

AD[33]

Gnd

AD[32]

13

AD[38]

Gnd

+Vio (1)

AD[37]

AD[36]

12

AD[42]

AD[41]

AD[40]

Gnd

AD[39]

11

AD[45]

Gnd

+Vio (1)

AD[44]

AD[43]

10

AD[49]

AD[48]

AD[47]

Gnd

AD[46]

9

AD[52]

Gnd

+Vio (1)

AD[51]

AD[50]

8

AD[56]

AD[55]

AD[54]

Gnd

AD[53]

7

AD[59]

Gnd

+Vio (1)

AD[58]

AD[57]

6

AD[63]

AD[62]

AD[61]

Gnd

AD[60]

5

C/BE[5]

Gnd

+Vio (1)

C/BE[4]

PAR64

4

+Vio (1)

Bus Res

C/BE[7]

Gnd

C/BE[6]

3

CLK4 (3)

Gnd

GNT3# (3)

REQ4# (3)

GNT4# (3)

2

CLK2 (3)

CLK3 (3)

SYSEN#

GNT2# (3)

REQ3# (3)

1

CLK1 (3)

Gnd

REQ1# (3)

GNT1# (3)

REQ2# (3)


Posted in Compact PCI Connectors - P2

May 7, 2012
6:16 pm
by: admin

Query Slot Status

Parameters passed: Logical Slot identifier

Parameters returned: Slot state {on, off}

Board power requirement {not present, low, medium, high}

Board frequency capability {33 MHz, 66 MHz, insufficient power}

Slot frequency {33 MHz, 66 MHz}

This request returns the state of a hot plug slot and any board that may be plugged in. The Hot Plug System Driver determines a board’s frequency capability either by reading M66EN or the 66 MHz CAPABLE bit in the Configuration Header. The driver will return an indication of insufficient power if it must read the Configuration Header but is unable to turn on the slot due to insufficient power.

Posted in Query Slot Status

May 7, 2012
6:16 pm
by: admin

Set Slot Status

Logical slot identifier New state {off, on}

New Attention Indicator state {normal, attention}

Completion status {successful, wrong frequency, insufficient power, insufficient configuration resources, power failure, general failure}

This request controls the state of a hot plug slot and its associated Attention Indicator. For purposes of this primitive, a slot has only two states: on or off. In the on state the slot is powered and con­nected to the bus. In the off state it is not powered, isolated from the bus and RST# is asserted.

If the request fails, the Hot Plug System Driver should leave the slot in the off state unless otherwise indicated. Possible failures include:

¦ Wrong Frequency. A 33 MHz board was plugged into a bus segment operating at 66 MHz.

¦ Insufficient Power. By reading PRSNT[2::1], the Hot Plug System Driver has determined that there is not enough power left to turn on this slot.

¦ Insufficient Configuration Resources. If the Hot Plug System Driver is responsible for running the configuration routine, it may return this error if there are not enough resources available to configure the board. The slot may be left on

Parameters passed:

Parameters returned:

If the operating system can tolerate a partially configured board.

¦ Power Failure. A power fault, i. e. short, was detected in the slot.

¦ General Failure. Any condition not otherwise covered.

Posted in Set Slot Status